Baffa-1 Hardware
The Baffa-1 was built from scratch using 74-Series logic gates and constructed using custom printed circuit boards. The main project has 221 chips and each peripheral board may have more 3 to 10 ICs!
Some of the project requirements are:
Some of the project requirements are:
- Support for user and kernel priviledge modes, with up to 256 processes running in parallel.
- Support for paged virtual memory, such that each process can have a total of 64KB RAM for itself.
- Two serial ports (16550), a real time clock(M48T02), 2 parallel ports(8255), a programmable timer(8253), an IDE hard-drive interface(2.5 Inch HDD), and a soundboard(AY-3-8910).
- The CPU supports 8 prioritized external interrupts, and a DMA channel.
- The sequencer is microcoded, with 15 ROMS operating horizontally.
- It has 401 instructions implemented, and up to 768 possible by using escape codes.
- Support for 8/16-Bit MUL and DIV instructions.
- Fast indexed string instructions in the spirit of x86's (REP) MOVSB, CMPSB, LODSB, STOSB, etc
REGISTER TABLE
| General Purpose Registers | ||
| A | AH/AL | Accumulator |
| B | BH/BL | Base Register (Secondary Counter Register) |
| C | CH/CL | Counter Register (Primary Counter) |
| D | DH/DL | Data Register / Data Pointer |
| G | GH/GL | General Register (For scratch) |
| Special Purpose Registers | ||
| PC | - | Program Counter |
| SP | - | Stack Pointer |
| SSP | - | Supervisor Stack Pointer |
| BP | - | Base Pointer (Used to manage stack frames) |
| SI | - | Source Index (Source address for string operations) |
| DI | - | Destination Index (Destination address for string operations) |
| TDR | TDRH/TDRL | Temporary Data Register |
| PTB | - | Page Table Base |
| MSW | Flags/Status | Machine Status Word |
CPU ARCHITECTURE
Baffa-1 Schematics